Static random access memory (SRAM) is an important type of memory. FIG. 1 is a typical configuration of SRAM. The SRAM cell in FIG. 1 is a basic unit for storing logic value in a SRAM chip and is selected via WLn, and data write and data read are conducted via two bitlines BL and BLb. During read operation, the SRAM cell outputs a pair of complementary signals on BL and BLb, that is, potential of BL is higher than that of BLb, or potential of BL is lower than that of BLb, thereby indicating logic value 0 or 1 stored in that SRAM cell.
Potential difference between the complementary signals on BL and BLb is relatively small, it is only several tens to one hundred millivolts (mVs) in general, and is much smaller than potential difference between logic high level and logic low level in a typical digital circuit. Therefore, driving capability of a SRAM cell itself is limited, and can not meet the requirement of driving post-stage logic circuit. A sense amplifier is used to process signals output on BL and BLb. The sense amplifier is generally multiplexed by a plurality of SRAM cells. Outputs of these SRAM cells, i.e. BL and BLb in FIG. 1, are connected to inputs of the sense amplifier, i.e. DLT and DLC in FIG. 1, via a bitline selection switch circuit. The sense amplifier performs differential amplification on the two inputted signals and then outputs the amplified signal. For example, if signal level on DLT is higher than that on DLC, an output terminal OUT of the sense amplifier outputs logic high level; if signal level on DLT is lower than that on DLC, the output terminal OUT of the sense amplifier outputs logic low level. Driving capability of the sense amplifier is stronger and thus can drive post-stage logic circuit.
Signal outputted from the sense amplifier reaches an output pin of a chip via a global data bus GBL. For a high density SRAM device, GBL is relatively long, thereby having large parasitic resistance and parasitic capacitance. Accordingly, the delay from sense amplifier establishing a stable output to pin of the chip establishing a stable output is also relatively long. This affects improvement in SRAM speed. Thus, there is a need to reduce the delay.